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110 MSPS/140 MSPS Analog Interface for Flat Panel Displays AD9985A
FEATURES
Variable analog input bandwidth control Variable SOGIN bandwidth control Automated clamping level adjustment 140 MSPS maximum conversion rate 300 MHz analog bandwidth 0.5 V to 1.0 V analog input range 500 ps p-p PLL clock jitter at 110 MSPS 3.3 V power supply Full sync processing Selectable input filtering Sync detect for hot plugging Midscale clamping Power-down mode Low power: 500 mW typical 4:2:2 output format mode
FUNCTIONAL BLOCK DIAGRAM
AUTO-CLAMP LEVEL ADJUST 8
RIN
CLAMP
A/D
ROUTA
AUTO-CLAMP LEVEL ADJUST 8
GIN
CLAMP
A/D
GOUTA
AUTO-CLAMP LEVEL ADJUST 8
BIN HSYNC COAST CLAMP
CLAMP
A/D
BOUTA MIDSCV
APPLICATIONS
RGB graphics processing LCD monitors and projectors Plasma display panels Scan converters Microdisplays Digital TVs
FILT SOGIN
SYNC PROCESSING AND CLOCK GENERATION
DTACK HSOUT VSOUT SOGOUT REF REF BYPASS
SCL SDA A0 SERIAL REGISTER AND POWER MANAGEMENT
Figure 1.
GENERAL DESCRIPTION
The AD9985A is a complete 8-bit, 140 MSPS, monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz support resolutions up to SXGA (1280 x 1024 at 75 Hz). The AD9985A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and horizontal sync (Hsync) and Coast signals. Three-state CMOS outputs can be powered from 2.5 V to 3.3 V. The AD9985A's on-chip PLL generates a pixel clock from the Hsync input. Pixel clock output frequencies range from 12 MHz to 140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the Coast signal is presented, the PLL maintains its output frequency in the absence of Hsync. A sampling phase adjustment is provided. Data, Hsync, and clock output phase relationships are maintained. The AD9985A also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or can be provided by the user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface. Fabricated in an advanced CMOS process, the AD9985A is provided in a space-saving 80-lead LQFP surface-mount Pb-free plastic package, and is specified over the -40C to +85C temperature range.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
05484-001
AD9985A
AD9985A TABLE OF CONTENTS
Specifications..................................................................................... 3 Explanation of Test Levels ........................................................... 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Design Guide................................................................................... 11 General Description................................................................... 11 Digital Inputs .............................................................................. 11 Input Signal Handling................................................................ 11 Hsync, Vsync Inputs .................................................................. 11 Serial Control Port ..................................................................... 11 Output Signal Handling............................................................. 11 Clamping ..................................................................................... 11 RGB Clamping........................................................................ 11 YUV Clamping ....................................................................... 12 Gain and Offset Control............................................................ 12 Auto Offset .............................................................................. 12 Sync-on-Green............................................................................ 13 Clock Generation ....................................................................... 13 12-Bit Divisor Register .......................................................... 14 2-Bit VCO Range Register .................................................... 14 3-Bit Charge Pump Current Register .................................. 14 5-Bit Phase Adjust Register................................................... 14 Power Management.................................................................... 14 Timing.......................................................................................... 15 Hsync Timing ............................................................................. 15 Coast Timing .............................................................................. 16 2-Wire Serial Register Map ........................................................... 17 2-Wire Serial Control Register Detail Chip Identification ... 19 PLL Divider Control .................................................................. 19 Clock Generator Control .......................................................... 20 Clamp Timing............................................................................. 20 Hsync Pulse Width..................................................................... 20 Input Gain ................................................................................... 20 Input Offset ................................................................................. 21 Mode Control 1 .......................................................................... 21 2-Wire Serial Control Port ............................................................ 26 Data Transfer via Serial Interface............................................. 26 Sync Slicer.................................................................................... 28 Sync Separator ............................................................................ 28 PCB Layout Recommendations.................................................... 29 Analog Interface Inputs ............................................................. 29 Power Supply Bypassing ............................................................ 29 PLL ............................................................................................... 29 Outputs (Both Data and Clocks).............................................. 30 Digital Inputs .............................................................................. 30 Voltage Reference ....................................................................... 30 Outline Dimensions ....................................................................... 31 Ordering GuIde .......................................................................... 31
REVISION HISTORY
7/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD9985A SPECIFICATIONS
VD = 3.3 V, VDD = 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted. Table 1.
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity No Missing Codes ANALOG INPUT Input Voltage Range Minimum Maximum Gain Tempco Input Bias Current Input Offset Voltage Input Full-Scale Matching Offset Adjustment Range REFERENCE OUTPUT Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Data to Clock Skew tBUFF tSTAH tDHO tDAL tDAH tDSU tSTASU tSTOTSU HSYNC Input Frequency Maximum PLL Clock Rate Minimum PLL Clock Rate PLL Jitter Sampling Phase Tempco DIGITAL INPUTS Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Current, High (VIH) Input Current, Low (VIL) Input Capacitance Temp Test Level Min AD9985AKSTZ-110 Typ Max 8 0.5 +1.25/-1.0 +1.35/-1.0 0.5 1.85 2.0 Guaranteed Min AD9985AKSTZ-140 Typ Max 8 0.5 +1.35/-1.0 1.45/-1.0 0.5 2.0 2.3 Guaranteed Unit Bits LSB LSB LSB LSB
25C Full 25C Full Full
I VI I VI VI
Full Full 25C 25C Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25C Full Full Full Full Full Full 25C
VI VI V IV IV V VI VI V V VI IV IV VI VI VI VI VI VI VI VI IV VI IV IV IV IV VI VI V V V
0.5 1.0 100 1 1 7 1.5 49 1.25 50 110 -0.5 4.7 4.0 300 4.7 4.0 250 4.7 4.0 15 110 400 15 2.5 0.8 -1.0 +1.0 3 3 2.5 10 +2.0 140 -0.5 4.7 4.0 300 4.7 4.0 250 4.7 4.0 15 140 400 400 15 8.0 52 7 1.5 49 1.25 50 1.0 100
0.5
1 1 8.0 52
46
46
V p-p V p-p ppm/C A A mV %FS %FS V ppm/C MSPS MSPS ns s s ns s s ns s s kHz MHz MHz ps p-p ps p-p ps/C V V A A pF
10 +2.0
110 12 700 1 10001
110 12 7001 7001
0.8 -1.0 +1.0
Rev. 0 | Page 3 of 32
AD9985A
Parameter DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, Low (VOL) Duty Cycle DATACK Output Coding POWER SUPPLY VD Supply Voltage VDD Supply Voltage PVD Supply Voltage ID Supply Current (VD) IDD Supply Current (VDD) 2 IPVD Supply Current (PVD) Total Power Dissipation Power-Down Supply Current Power-Down Dissipation DYNAMIC PERFORMANCE Analog Bandwidth, Full Power Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 40.7 MHz Crosstalk THERMAL CHARACTERISTICS JC Junction-to-Case Thermal Resistance JA Junction-to-Ambient Thermal Resistance
1 2
Temp Full Full Full
Test Level VI VI IV
Min
AD9985AKSTZ-110 Typ Max
Min
AD9985AKSTZ-140 Typ Max
Unit V V %
VD - 0.1 45 50 Binary 3.3 3.3 3.3 132 19 8 525 5 16.5 300 2 1.5 44 43 55 0.1 55
VD - 0.1 45 50 Binary 3.3 3.3 3.3 180 26 11 650 5 16.5 300 2 1.5 43 42 55 0.1 55
Full Full Full 25C 25C 25C Full Full Full 25C 25C 25C 25C Full Full
IV IV IV V V V VI VI VI V V V V V V
3.15 2.2 3.15
3.45 3.45 3.45
3.15 2.2 3.15
3.45 3.45 3.45
760 15 50
900 15 50
V V V mA mA mA mW mA mW MHz ns ns dB dB dBc
V V
16 35
16 35
C/W C/W
VCO range = 10, charge pump current = 110, PLL divider = 1693. DATACK load = 15 pF, data load = 5 pF.
Rev. 0 | Page 4 of 32
AD9985A
VD = 3.3 V, VDD = 3.3 V, ADC clock = maximum conversion rate, unless otherwise noted. Table 2.
Parameter RESOLUTION DC ACCURACY Differential Nonlinearity Integral Nonlinearity ANALOG INPUT Input Voltage Range Minimum Maximum Gain Tempco Input Bias Current Input Offset Voltage Input Full-Scale Matching Offset Adjustment Range REFERENCE OUTPUT Output Voltage Temperature Coefficient SWITCHING PERFORMANCE Maximum Conversion Rate Minimum Conversion Rate Data-to-Clock Skew tBUFF tSTAH tDHO tDAL tDAH tDSU tSTASU tSTAH HSYNC Input Frequency Maximum PLL Clock Rate Minimum PLL Clock Rate PLL Jitter Sampling Phase Tempco DIGITAL INPUTS Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Current, High (IIH) Input Current, Low (IIL) Input Capacitance DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, Low (VOL) Duty Cycle, DATACK Output Coding Temp Test Level Min AD9985ABSTZ-110 Typ Max 8 0.5 0.5 +1.25/-1.0 +1.5/-1.0 1.85 3.2 Unit Bits LSB LSB LSB LSB
25C Full 25C Full
I VI I VI
Full Full 25C 25C Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25C Full Full Full Full Full Full 25C Full Full Full
VI VI V IV IV VI VI VI VI V VI IV IV VI VI VI VI VI VI VI VI IV VI IV IV IV IV VI VI V V V VI VI IV
0.5 1.0 100 1 2 7 1.5 49 1.25 100 110 -0.5 4.7 4.0 300 4.7 4.0 250 4.7 15 110 400 15 2.5 0.8 -1.0 1.0 3 VD - 0.1 45 50 Binary 0.1 55 10 +2.0 8.0 52
46
V p-p V p-p ppm/C A A mV % FS % FS V ppm/C MSPS MSPS ns s s ns s s ns s s kHz MHz MHz ps p-p ps p-p ps/C V V A A pF V V %
110 12 700 1 10001
Rev. 0 | Page 5 of 32
AD9985A
Parameter POWER SUPPLY VD Supply Voltage VDD Supply Voltage PVD Supply Voltage ID Supply Current (VD) IDD Supply Current (VDD) 2 IPVD Supply Current (PVD) Total Power Dissipation Power-Down Supply Current Power-Down Dissipation DYNAMIC PERFORMANCE Analog Bandwidth, Full Power Transient Response Overvoltage Recovery Time Signal-to-Noise Ratio (SNR) (Without Harmonics) fIN = 40.7 MHz Crosstalk THERMAL CHARACTERISTICS JC Junction-to-Case Thermal Resistance JA Junction-to-Ambient Thermal Resistance
1 2
Temp Full Full Full 25C 25C 25C Full Full Full 25C 25C 25C 25C Full Full
Test Level IV IV IV V V V VI VI VI V V V V V V
Min 3.15 2.2 3.15
AD9985ABSTZ-110 Typ Max 3.3 3.3 3.3 132 19 8 525 5 16.5 300 2 1.5 44 43 55 3.45 3.45 3.45
Unit V V V mA mA mA mW mA mW MHz ns ns dB dB dBc
760 15 50
V V
16 35
C/W C/W
VCO range = 10, charge pump current = 110, PLL divider = 1693. DATACK load = 15 pF, data load = 5 pF.
EXPLANATION OF TEST LEVELS
I. II. III. IV. V. VI.
100% production tested.
100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C; guaranteed by design and characterization testing.
Rev. 0 | Page 6 of 32
AD9985A ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter VD VDD Analog Inputs Digital Inputs Digital Output Current Operating Temperature Storage Temperature Maximum Junction Temperature Maximum Case Temperature Rating 3.6 V 3.6 V VD to 0.0 V 5 V to 0.0 V 20 mA -40C to +85C -65C to +150C 150C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 7 of 32
AD9985A PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
SOGOUT DATACK RED <0> RED <1> RED <2> RED <3> RED <4> RED <5> RED <6> RED <7> HSOUT VSOUT GND GND GND GND
60 PIN 1 59 58 57 56 55 54
VDD
VDD
VDD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
GND 1 GREEN <7> 2 GREEN <6> 3 GREEN <5> 4 GREEN <4> 5 GREEN <3> 6 GREEN <2> 7 GREEN <1> 8 GREEN <0> 9 GND 10 VDD 11 BLUE <7> 12 BLUE <6> 13 BLUE <5> 14 BLUE <4> 15 BLUE <3> 16 BLUE <2> 17 BLUE <1> 18 BLUE <0> 19 GND 20
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
VD
GND VD REF BYPASS SDA SCL A0 RIN GND VD VD GND SOGIN GIN GND VD VD GND BIN VD GND
AD9985A
TOP VIEW (Not to Scale)
53 52 51 50 49 48 47 46 45 44 43 42 41
HSYNC
VSYNC
GND
GND
GND
GND
GND
GND
COAST
MIDSCV
CLAMP
GND
VD
VD
PVD
PVD
VDD
VDD
FILT
VD
Figure 2. Pin Configuration
Table 4. Complete Pinout List
Pin Type Inputs Mnemonic RIN GIN BBIN HSYNC VSYNC SOGIN CLAMP COAST Red [7:0] Green [7:0] Blue [7:0] DATACK HSOUT VSOUT SOGOUT REF BYPASS MIDSCV FILT Function Analog Input for Converter R Analog Input for Converter G Analog Input for Converter B Horizontal SYNC Input Vertical SYNC Input Input for Sync-on-Green Clamp Input (External Clamp Signal) PLL Coast Signal Input Outputs of Converter Red, Bit 7 is the MSB Outputs of Converter Green, Bit 7 is the MSB Outputs of Converter Blue, Bit 7 is the MSB Data Output Clock HSYNC Output (Phase-Aligned with DATACK) VSYNC Output (Phase-Aligned with DATACK) Sync-on-Green Slicer Output Internal Reference Bypass Internal Midscale Voltage Bypass Connection for External Filter Components for Internal PLL Value 0.0 V to 1.0 V 0.0 V to 1.0 V 0.0 V to 1.0 V 3.3 V CMOS 3.3 V CMOS 0.0 V to 1.0 V 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS 1.25 V Pin No. 54 48 43 30 31 49 38 29 70 to 77 2 to 9 12 to 19 67 66 64 65 58 37 33
Outputs
References
Rev. 0 | Page 8 of 32
05484-002
AD9985A
Pin Type Power Supply Mnemonic VD VDD PVD GND SDA SCL A0 Function Analog Power Supply Output Power Supply PLL Power Supply Ground Serial Port Data I/O Serial Port Data Clock (100 kHz maximum) Serial Port Address Input 1 Value 3.3 V 3.3 V 3.3 V 0V 3.3 V CMOS 3.3 V CMOS 3.3 V CMOS Pin No. 26, 27, 39, 42, 45, 46, 51, 52, 59, 62 11, 22, 23, 69, 78, 79 34, 35 1, 10, 20, 21, 24, 25, 28, 32, 36, 40, 41, 44, 47, 50, 53, 60, 61, 63, 68, 80 57 56 55
Serial Port (2-Wire)
Table 5. Pin Function Descriptions
Pin Inputs RIN GIN BBIN Description Analog Input for Red Channel. Analog Input for Green Channel. Analog Input for Blue Channel. High impedance inputs that accept the red, green, and blue channel graphics signals, respectively. (The three channels are identical, and can be used for any colors, but colors are assigned for convenient reference.) They accommodate input signals ranging from 0.5 V to 1.0 V full scale. Signals should be ac-coupled to these pins to support clamp operation. Horizontal Sync Input. This input receives a logic signal that establishes the horizontal timing reference and provides the frequency reference for pixel clock generation. The logic sense of this pin is controlled by serial Register 0x0E, Bit 6 (Hsync polarity). Only the leading edge of Hsync is active; the trailing edge is ignored. When Hsync polarity = 0, the falling edge of Hsync is used. When Hsync polarity = 1, the rising edge is active. The input includes a Schmitt trigger for noise immunity, with a nominal input threshold of 1.5 V. Vertical Sync Input. This is the input for vertical sync. Sync-on-Green Input. This input is provided to assist with processing signals with embedded sync, typically on the green channel. The pin is connected to a high speed comparator with an internally generated threshold. The threshold level can be programmed in 10 mV steps to any voltage between 10 mV and 330 mV above the negative peak of the input signal. The default voltage threshold is 150 mV. When connected to an ac-coupled graphics signal with embedded sync, it produces a noninverting digital output on SOGOUT. (This is usually a composite sync signal, containing both vertical and horizontal sync information that must be separated before passing the horizontal sync signal to Hsync.) When not used, this input should be left unconnected. For more details on this function and how it should be configured, refer to the Sync-on-Green section. External Clamp Input. This logic input can be used to define the time during which the input signal is clamped to ground. It should be exercised when the reference dc level is known to be present on the analog input channels, typically during the back porch of the graphics signal. The CLAMP pin is enabled by setting control bit clamp function to 1, (Register 0x0F, Bit 7, default is 0). When disabled, this pin is ignored and the clamp timing is determined internally by counting a delay and duration from the trailing edge of the Hsync input. The logic sense of this pin is controlled by clamp polarity Register 0x0F, Bit 6. When not used, this pin must be grounded and clamp function programmed to 0. Clock Generator Coast Input (Optional). This input can be used to cause the pixel clock generator to stop synchronizing with Hsync and continue producing a clock at its current frequency and phase. This is useful when processing signals from sources that fail to produce horizontal sync pulses during the vertical interval. The Coast signal is generally not required for PC-generated signals. The logic sense of this pin is controlled by Coast polarity (Register 0x0F, Bit 3). When not used, this pin can be grounded and Coast polarity programmed to 1, or tied high (to VD through a 10 k resistor) and Coast polarity programmed to 0. Coast polarity defaults to 1 at power-up. Horizontal Sync Output. A reconstructed and phase-aligned version of the Hsync input. Both the polarity and duration of this output can be programmed via serial bus registers. By maintaining alignment with DATACK and Data outputs, data timing with respect to horizontal sync can always be determined. Vertical Sync Output. A reconstructed and phase-aligned version of the video Vsync. The polarity of this output can be controlled via a serial bus bit. The placement and duration in all modes is set by the graphics transmitter. Sync-on-Green Slicer Output. This pin outputs either the signal from the sync-on-green slicer comparator or an unprocessed but delayed version of the Hsync input. See the sync processing block diagram (Figure 14) to view how this pin is connected. (Apart from slicing off SOG, the output from this pin gets no other additional processing on the AD9985A. Vsync separation is performed via the sync separator.)
HSYNC
VSYNC SOGIN
CLAMP
COAST
Outputs HSOUT
VSOUT SOGOUT
Rev. 0 | Page 9 of 32
AD9985A
Pin Data Outputs RED GREEN BLUE Description Data Output, Red Channel. Data Output, Green Channel. Data Output, Blue Channel. The main data outputs. Bit 7 is the MSB. The delay from pixel sampling time to output is fixed. When the sampling time is changed by adjusting the phase register, the output timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing relationship among the signals is maintained. For exact timing information, refer to Figure 9, Figure 10, and Figure 11. Data Output Clock. This is the main clock output signal used to strobe the output data and HSOUT into external logic. It is produced by the internal clock generator and is synchronous with the internal pixel sampling clock. When the sampling time is changed by adjusting the phase register, the output timing is shifted as well. The Data, DATACK, and HSOUT outputs are all moved, so the timing relationship among the signals is maintained. Internal Reference Bypass. Bypass for the internal 1.25 V band gap reference. It should be connected to ground through a 0.1 F capacitor. The absolute accuracy of this reference is 4%, and the temperature coefficient is 50 ppm, which is adequate for most AD9985A applications. If higher accuracy is required, an external reference can be used instead. Midscale Voltage Reference Bypass. Bypass for the internal midscale voltage reference. It should be connected to ground through a 0.1 F capacitor. The exact voltage varies with the gain setting of the blue channel. External Filter Connection. For proper operation, the pixel clock generator PLL requires an external filter. Connect the filter shown in Figure 6 to this pin. For optimal performance, minimize noise and parasitics on this node. Main Power Supply. These pins supply power to the main elements of the circuit. They should be filtered and kept as quiet as possible. Digital Output Power Supply. A large number of output pins (up to 25) switching at high speed (up to 110 MHz) generates a lot of power supply transients (noise). These supply pins are identified separately from the VD pins so special care can be taken to minimize output noise transferred into the sensitive analog circuitry. If the AD9985A is interfacing with lower voltage logic, VDD can be connected to a lower supply voltage (as low as 2.5 V) for compatibility. Clock Generator Power Supply. The most sensitive portion of the AD9985A is the clock generation circuitry. These pins provide power to the clock PLL and help the user design for optimal performance. The designer should provide quiet, noise-free power to these pins. Ground. The ground return for all circuitry on-chip. It is recommended that the AD9985A be assembled on a single solid ground plane, with careful attention given to ground current paths. Serial Port Data I/O. Serial Port Data Clock. Serial Port Address Input 1. For a full description of the 2-wire serial register and how it works, refer to the 2-Wire Serial Control Port section.
Data Clock Output DATACK
References REF BYPASS
MIDSCV FILT Power Supply VD VDD
PVD
GND Serial Port (2-Wire) SDA SCL A0
Rev. 0 | Page 10 of 32
AD9985A DESIGN GUIDE
GENERAL DESCRIPTION
The AD9985A is a fully integrated solution for capturing analog RGB signals and digitizing them for display on flat panel monitors or projectors. The circuit is ideal for providing a computer interface for HDTV monitors or as the front end to high performance video scan converters. Implemented in a high performance CMOS process, the interface can capture signals with pixel rates up to 110 MHz. The AD9985A includes all necessary input buffering, signal dc restoration (clamping), offset and gain (brightness and contrast) adjustment, pixel clock generation, sampling phase control, and output data formatting. All controls are programmable via a 2-wire serial interface. Full integration of these sensitive analog functions makes system design straightforward and less sensitive to the physical and electrical environment. With a typical power dissipation of only 500 mW and an operating temperature range of 0C to 70C (-40C to +85C for the AD9985ABST), the device requires no special environmental considerations. is effective in rolling off the input bandwidth slightly and providing a high quality signal over a wider range of conditions. Using a Fair-Rite #2508051217Z0 High Speed Signal Chip Bead inductor in the circuit of Figure 3 yields good results in most applications.
RGB INPUT 75 47nF RIN GIN BIN
Figure 3. Analog Input Interface Circuit
HSYNC, VSYNC INPUTS
The interface also takes a horizontal sync signal, which is used to generate the pixel clock and clamp timing. This can be either a sync signal directly from the graphics source, or a preprocessed TTL or CMOS level signal. The Hsync input includes a Schmitt trigger buffer for immunity to noise and signals with long rise times. In typical PC-based graphic systems, the sync signals are simply TTL-level drivers feeding unshielded wires in the monitor cable. As such, no termination is required.
DIGITAL INPUTS
All digital inputs on the AD9985A operate to 3.3 V CMOS levels. However, all digital inputs are 5 V tolerant. Applying 5 V to them does not cause any damage.
SERIAL CONTROL PORT
The serial control port is designed for 3.3 V logic. If there are 5 V drivers on the bus, these pins should be protected with 150 series resistors placed between the pull-up resistors and the input pins.
INPUT SIGNAL HANDLING
The AD9985A has one high impedance analog input pin for each of the red, green, and blue channels. They accommodate signals ranging from 0.5 V to 1.0 V p-p. Signals are typically brought onto the interface board via a DVI-I connector, a 15-pin D connector, or via BNC connectors. The AD9985A should be located as close as practical to the input connector. Signals should be routed via matchedimpedance traces (normally 75 ) to the IC input pins. At this point, the signal should be resistively terminated (75 to the signal ground return) and capacitively coupled to the AD9985A inputs through 47 nF capacitors. These capacitors form part of the dc restoration circuit. When impedances are perfectly matched, the best performance can be obtained with the widest possible signal bandwidth. The ultrawide bandwidth inputs of the AD9985A (300 MHz) can track the input signal continuously as it moves from one pixel level to the next, and digitize the pixel during a long, flat pixel time. In many systems, however, there are mismatches, reflections, and noise, which can result in excessive ringing and distortion of the input waveform. This makes it more difficult to establish a sampling phase that provides good image quality. It has been shown that a small inductor in series with the input
OUTPUT SIGNAL HANDLING
The digital outputs are designed and specified to operate from a 3.3 V power supply (VDD). They can also work with a VDD as low as 2.5 V for compatibility with other 2.5 V logic.
CLAMPING
RGB Clamping
To properly digitize the incoming signal, the dc offset of the input must be adjusted to fit the range of the on-board ADCs. Most graphics systems produce RGB signals with black at ground and white at approximately 0.75 V. However, if sync signals are embedded in the graphics, the sync tip is often at ground, black is at 300 mV, and white is at approximately 1.0 V. Some common RGB line amplifier boxes use emitter-follower buffers to split signals and increase drive capability. This introduces a 700 mV dc offset to the signal, which must be removed for proper capture by the AD9985A. The key to clamping is to identify a portion (time) of the signal when the graphic system is known to be producing black. An offset is then introduced that results in the ADCs producing a
Rev. 0 | Page 11 of 32
05484-003
AD9985A
black output (code 0x00) when the known black input is present. The offset then remains in place when other signal levels are processed, and the entire signal is shifted to eliminate offset errors. In most PC graphics systems, black is transmitted between active video lines. With CRT displays, when the electron beam has completed writing a horizontal line on the screen (at the right side), the beam is deflected quickly to the left side of the screen (called horizontal retrace), and a black signal is provided to prevent the beam from disturbing the image. In systems with embedded sync, a blacker-than-black signal (Hsync) is produced briefly to signal the CRT that it is time to begin a retrace. For obvious reasons, it is important to avoid clamping on the tip of Hsync. Fortunately, there is virtually always a period following Hsync, called the back porch, when a good black reference is provided. This is the time when clamping should be performed. The clamp timing can be established by simply exercising the CLAMP pin at the appropriate time (with External Clamp = 1). The polarity of this signal is set by the clamp polarity bit. A simpler method of clamp timing uses the AD9985A internal clamp timing generator. The clamp placement register is programmed with the number of pixel times that should pass after the trailing edge of Hsync before clamping starts. A second register (clamp duration) sets the duration of the clamp. These are both 8-bit values, which provide considerable flexibility in clamp generation. The clamp timing is referenced to the trailing edge of Hsync because, though Hsync duration can vary widely, the back porch (black reference) always follows Hsync. A good starting point for establishing clamping is to set the clamp placement to 0x09 (providing 9 pixel periods for the graphics signal to stabilize after sync) and set the clamp duration to 0x14 (giving the clamp 20 pixel periods to re-establish the black reference). Clamping is accomplished by placing an appropriate charge on the external input coupling capacitor. The value of this capacitor affects the performance of the clamp. If it is too small, there is a significant amplitude change during a horizontal line time (between clamping intervals). If the capacitor is too large, it takes excessively long for the clamp to recover from a large change in incoming signal offset. The recommended value (47 nF) results in recovering from a step error of 100 mV to within 1/2 LSB in 10 lines with a clamp duration of 20 pixel periods on a 60 Hz SXGA signal. range of the ADC range (0x80) rather than at the bottom of the ADC converter range (0x00). Clamping to midscale rather than to ground can be accomplished by setting the clamp select bits in the serial bus register. Each of the three converters has its own selection bit so that they can be clamped to either midscale or ground independently. These bits are located in Register 0x10, Bits [2:0]. The midscale reference voltage that each ADC clamps to is provided on the MIDSCV pin (Pin 37). This pin should be bypassed to ground with a 0.1 F capacitor, even if midscale clamping is not required.
GAIN AND OFFSET CONTROL
The AD9985A can accommodate input signals with inputs ranging from 0.5 V to 1.0 V full scale. The full-scale range is set in three 8-bit registers (red gain, green gain, and blue gain). Note that increasing the gain setting results in an image with less contrast. The offset control shifts the entire input range, resulting in a change in image brightness. Three 7-bit registers (red offset, green offset, blue offset) provide independent settings for each channel. The offset controls provide a 63 LSB adjustment range. This range is connected with the full-scale range, so if the input range is doubled (from 0.5 V to 1.0 V), the offset step size is also doubled (from 2 mV per step to 4 mV per step). Figure 4 shows the interaction of gain and offset controls. The magnitude of an LSB in offset adjustment is proportional to the full-scale range, so changing the full-scale range also changes the offset. The change is minimal if the offset setting is near midscale. When changing the offset, the full-scale range is not affected, but the full-scale level is shifted by the same amount as the zero-scale level.
OFFSET = 7FH OFFSET = 3FH 1.0
INPUT RANGE (V)
OFFSET = 00H
0.5 OFFSET = 7FH
0
OFFSET = 3FH
OFFSET = 00H 00H GAIN FFH
05484-004
YUV Clamping
YUV graphics signals are slightly different from RGB signals, as the dc reference level (black level in RGB signals) can be at the midpoint of the graphics signal rather than at the bottom. For these signals, it might be necessary to clamp to the midscale
Figure 4. Gain and Offset Control
Auto Offset
In addition to the manual offset adjustment mode (via registers 0x0B to 0x0D), the AD9985A also includes circuitry to automatically calibrate the offset for each channel. By monitoring
Rev. 0 | Page 12 of 32
AD9985A
the output of each ADC during the back porch of the input signals, the AD9985A can self-adjust to eliminate any offset errors in its own ADC channels, as well as any offset errors present on the incoming graphics or video signals. To activate the auto offset mode, set Register 0x1D, Bit 7 to 1. Next, the target code registers (0x19 through 0x1B) must be programmed. The values programmed into the target code registers should be the output code desired from the AD9985A during the back porch reference time. For example, for RGB signals, all three registers are normally programmed to code 1, while for YPbPr signals, the green (Y) channel is normally programmed to code 1, and the blue and red channels (Pb and Pr) are normally set to 128. Any target code value between 1 and 254 can be set, although the AD9985A's offset range may not be able to reach every value. Intended target code values range from (but are not limited to) 1 to 40 when ground clamping, and 90 to 170 when midscale clamping. The ability to program a target code for each channel gives users a large degree of freedom and flexibility. While in most cases all channels are set either to 1 or 128, the flexibility to select other values allows the possibility of inserting intentional skews between channels. It also allows the ADC range to be skewed so that voltages outside of the normal range can be digitized. For example, setting the target code to 40 allows the sync tip, which is normally below black level, to be digitized and evaluated. Lastly, when in auto offset mode, the manual offset registers (0x0B to 0x0D) have new functionality. The values in these registers are digitally added to the value of the ADC output. The purpose of doing this is to match a benefit that is present with manual offset adjustment. Adjusting these registers is an easy way to make brightness adjustments. Although some signal range is lost with this method, it has proven to be a very popular function. In order to be able to increase and decrease brightness, the values in these registers in this mode are signed twos complement. The digital adder is only used in auto offset mode. Although it cannot be disabled, setting the offset registers to all 0s effectively disables it by always adding 0.
47nF RIN 47nF BIN 47nF GIN SOG
05484-005
1nF
Figure 5. Typical Clamp Configuration
CLOCK GENERATION
A phase-locked loop (PLL) is used to generate the pixel clock. In this PLL, the Hsync input provides a reference frequency. A voltage controlled oscillator (VCO) generates a much higher pixel clock frequency. This pixel clock is divided by the PLL divide value (Register 0x01 and Register 0x02) and phase compared with the Hsync input. Any error is used to shift the VCO frequency and maintain lock between the two signals. The stability of this clock is a very important element in providing the clearest and most stable image. During each pixel time, there is a period during which the signal is slewing from the old pixel amplitude and settling at its new value. Then, there is a time when the input voltage is stable before the signal must slew to a new value (Figure 6). The ratio of the slewing time to the stable time is a function of the bandwidth of the graphics DAC and the bandwidth of the transmission system (cable and termination). It is also a function of the overall pixel rate. Clearly, if the dynamic characteristics of the system remain fixed, the slewing and settling time is, likewise, fixed. This time must be subtracted from the total pixel period, leaving the stable period. At higher pixel frequencies, the total cycle time is shorter, and the stable pixel time also becomes shorter.
PIXEL CLOCK INVALID SAMPLE TIMES
SYNC-ON-GREEN
The sync-on-green input operates in two steps. First, it sets a baseline clamp level off of the incoming video signal with a negative peak detector. Second, it sets the sync trigger level to a programmable level (typically 150 mV) above the negative peak. The sync-on-green input must be ac-coupled to the green analog input through its own capacitor, as shown in Figure 5. The value of the capacitor must be 1 nF 20%. If sync-on-green is not used, this connection is not required. The sync-on-green signal is always negative polarity.
Figure 6. Pixel Sampling Times
Any jitter in the clock reduces the precision with which the sampling time can be determined, and must also be subtracted from the stable pixel time. Considerable care has been taken in the design of the AD9985A's clock generation circuit to minimize jitter. As shown in Figure 7, the clock jitter of the AD9985A is less than 5% of the total pixel time in all operating modes, making the reduction in the valid sampling time negligible due to jitter.
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05484-006
AD9985A
14
3-Bit Charge Pump Current Register
This register allows the current that drives the low-pass loop filter to be varied. The possible current values are listed in Table 7. Table 7. Charge Pump Current/Control Bits
Ip2 0 0 0 0 1 1 1 1 Ip1 0 0 1 1 0 0 1 1 Ip0 0 1 0 1 0 1 0 1 Current (A) 50 100 150 250 350 500 750 1500
12
PIXEL CLOCK JITTER (p-p) (%)
10
8 6
4
2 0
05484-007
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 FREQUENCY (MHz)
Figure 7. Pixel Clock Jitter vs. Frequency
5-Bit Phase Adjust Register
The phase of the generated sampling clock can be shifted to locate an optimum sampling point within a clock cycle. The phase adjust register provides 32 phase-shift steps of 11.25 each. The Hsync signal with an identical phase shift is available through the HSOUT pin. The COAST pin is used to allow the PLL to continue to run at the same frequency in the absence of the incoming Hsync signal or during disturbances in Hsync (such as equalization pulses). This can be used during the vertical sync period, or any other time that the Hsync signal is unavailable. The polarity of the Coast signal is set through the Coast polarity register. Also, the polarity of the Hsync signal is set through the Hsync polarity register. If not using automatic polarity detection, the Hsync and Coast polarity bits should be set to match the respective polarities of the input signals.
The PLL characteristics are determined by the loop filter design, the PLL charge pump current, and the VCO range setting. The loop filter design is shown in Figure 8. Recommended settings of VCO range and charge pump current for VESA standard display modes are listed in Table 9.
CP 0.0082F RZ 2.7k
05484-008
CZ 0.082F
PVD
FILT
Figure 8. PLL Loop Filter Detail
Four programmable registers are provided to optimize the performance of the PLL.
12-Bit Divisor Register
The input Hsync frequencies range from 15 kHz to 110 kHz. The PLL multiplies the frequency of the Hsync signal, producing pixel clock frequencies in the range of 12 MHz to 110 MHz. The divisor register controls the exact multiplication factor. This register can be set to any value between 221 and 4095. (The divide ratio that is actually used is the programmed divide ratio plus 1.)
POWER MANAGEMENT
The AD9985A uses the activity detect circuits, the active interface bits in the serial bus, the active interface override bits, and the power-down bit to determine the correct power state. The three power states are full-power, seek mode, and powerdown. Table 8 summarizes how the AD9985A determines which power mode to be in and which circuitry is powered on/off in each of these modes. The power-down command has priority over the automatic circuitry. Table 8. Power-Down Mode Descriptions
Mode FullPower Seek Mode PowerDown
1 2
2-Bit VCO Range Register
To improve the noise performance of the AD9985A, the VCO operating frequency range is divided into three overlapping regions. The VCO range register sets this operating range. Table 6 shows the frequency ranges for the lowest and highest regions. Table 6. VCO Frequency Ranges
PV1 0 0 1 1 PV0 0 1 0 1 Pixel Clock Range (MHz) AD9985AKSTZ AD9985ABSTZ 12 to 32 12 to 30 32 to 64 30 to 60 64 to 110 60 to 110 110 to 140
Inputs Power-Down 1 1 1
Sync Detect 2 1 0
Powered On or Comments Everything Serial Bus, Sync Activity Detect, SOG, Band Gap Reference Serial Bus, Sync Activity Detect, SOG, Band Gap Reference
0
X
Power-down is controlled via Bit 1 in Serial Bus Register 0x0F. Sync detect is determined by OR'ing Bits 7, 4, and 1 in Serial Bus Register 0x14.
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AD9985A
Table 9. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Standard Modes VGA Resolution 640 x 480 Refresh Rate 60 Hz 72 Hz 75 Hz 85 Hz 56 Hz 60 Hz 72 Hz 75 Hz 85 Hz 60 Hz 70 Hz 75 Hz 80 Hz 85 Hz 60 Hz 75 Hz 60Hz 60Hz 60Hz 60Hz Horizontal Frequency 31.5 kHz 37.7 kHz 37.5 kHz 43.3 kHz 35.1 kHz 37.9 kHz 48.1 kHz 46.9 kHz 53.7 kHz 48.4 kHz 56.5 kHz 60.0 kHz 64.0 kHz 68.3 kHz 64.0 kHz 80.0 kHz 15.75 kHz 31.47 kHz 45.0 kHz 33.75 kHz Pixel Rate 25.175 MHz 31.500 MHz 31.500 MHz 36.000 MHz 36.000 MHz 40.000 MHz 50.000 MHz 49.500 MHz 56.250 MHz 65.000 MHz 75.000 MHz 78.750 MHz 85.500 MHz 94.500 MHz 108.000 MHz 135.000 MHz 13.51MHz 27.00 MHz 74.25 MHz 74.25 MHz PLL Div 799 835 841 831 1025 1055 1039 1055 1047 1343 1327 1313 1335 1383 1687 1687 857 857 1649 2199 AD9985AKSTZ VCORNGE Current 00 110 00 110 00 110 01 100 01 100 01 100 01 101 01 101 01 101 10 101 10 100 10 100 10 101 10 101 10 110 11 110 00 00 10 10 011 110 100 100 AD9985ABSTZ VCORNGE Current 00 011 01 010 01 010 01 010 01 010 01 011 01 100 01 100 01 101 10 011 10 011 10 011 10 100 10 100 10 101
SVGA
800 x 600
XGA
1024 x 768
SXGA TV Modes 480i 480p 720p 1080i
1280 x 1024
720 x 480 720 x 483 1280 x 720 1920 x 1080
00 00 10 10
011 011 011 011
TIMING
The timing diagrams in this section show the operation of the AD9985A. The output data clock signal is created so that its rising edge always occurs between data transitions, and can be used to latch the output data externally. The pipeline in the AD9985A must be flushed before valid data becomes available. This means that four data sets are presented before valid data is available.
tPER tCYCLE
DATACK
Hsync TIMING
Hsync is processed in the AD9985A to eliminate ambiguity in the timing of the leading edge with respect to the phase-delayed pixel clock and data. The Hsync input is used as a reference to generate the pixel sampling clock. The sampling phase can be adjusted, with respect to Hsync, through a full 360 in 32 steps via the phase adjust register (to optimize the pixel sampling time). Display systems use Hsync to align memory and display write cycles; therefore, it is important to have a stable timing relationship between Hsync output (HSOUT) and data clock (DATACK). Three things happen to Horizontal Sync in the AD9985A. First, the polarity of Hsync input is determined and thus has a known output polarity. The known output polarity can be programmed either active high or active low (Register 0x0E, Bit 5). Second, HSOUT is aligned with DATACK and data outputs. Third, the duration of HSOUT (in pixel clocks) is set via Register 0x07. HSOUT is the sync signal that should be used to drive the rest of the display system.
tSKEW
05484-009
DATA HSOUT
Figure 9. Output Timing
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AD9985A
COAST TIMING
In most computer systems, the Hsync signal is provided continuously on a dedicated wire. In these systems, the Coast input and function are unnecessary and should not be used, and the pin should be permanently connected to the inactive state. In some systems, however, Hsync is disturbed during the vertical sync period (Vsync). In some cases, Hsync pulses disappear. In other systems, such as those that use composite sync (Csync) signals or embedded sync-on-green (SOG), Hsync includes equalization pulses or other distortions during Vsync. To avoid upsetting the clock generator during Vsync, it is
RGBIN HSYNC P0 P1 P2 P3 P4 P5 P6 P7
important to ignore these distortions. If the pixel clock PLL detects extraneous pulses, it attempts to lock to this new frequency, and changes frequency by the end of the Vsync period. It then takes a few lines of correct Hsync timing to recover at the beginning of a new frame, resulting in a tearing of the image at the top of the display. The Coast input is provided to eliminate this problem. It is an asynchronous input that disables the PLL input and allows the clock to free-run at its then-current frequency. The PLL can free-run for several lines without significant frequency drift.
PxCK HS 5-PIPE DELAY ADCCK
DATACK DOUTA HSOUT D0 D1 D2 D3 D4 D5 D6 D7
05484-010
.
VARIABLE DURATION
Figure 10. 4:4:4 Mode (For RGB and YUV)
RGBIN HSYNC
P0
P1
P2
P3
P4
P5
P6
P7
PxCK HS 5-PIPE DELAY ADCCK
DATACK GOUTA ROUTA Y0 U0 Y1 V1 Y2 U2 Y3 V3 Y4 U4 Y5 V5 Y6 U6 Y7 V7
05484-011
HSOUT
VARIABLE DURATION
Figure 11. 4:2:2 Mode (For YUV Only)
Rev. 0 | Page 16 of 32
AD9985A 2-WIRE SERIAL REGISTER MAP
The AD9985A is initialized and controlled by a set of registers that determine the operating modes. An external controller is used to write and read the control registers through the two-line serial interface port. Table 10. Control Register Map
Hexadecimal Address 0x00 0x01 1 Write and Read or Read-Only RO R/W Default Value 01101001 Register Name Chip Revision PLL Div MSB
Bits 7:0 7:0
0x021 0x03
R/W R/W
7:4 7:3
1101**** 01****** **001***
PLL Div LSB
0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
7:3 7:0 7:0 7:0 7:0 7:0 7:0 7:1 7:1 7:1 7:0
10000*** 10000000 10000000 00100000 10000000 10000000 10000000 1000000* 1000000* 1000000* 0******* *1****** **0***** ***0****
Phase Adjust Clamp Placement Clamp Duration Hsync Output Pulse Width Red Gain Green Gain Blue Gain Red Offset Green Offset Blue Offset Sync Control
Function An 8-bit register that represents the silicon revision level. This register is for Bits [11:4] of the PLL divider. Greater values mean the PLL operates at a faster rate. This register should be loaded first whenever a change is needed. This will give the PLL more time to lock. Bits [7:4] of this word are written to the LSBs [3:0] of the PLL divider word. Bits [7:6] VCO Range. Selects VCO frequency range. (See the PLL description.) Bits [5:3] Charge Pump Current. Varies the current that drives the low-pass filter. (See the PLL description.) ADC Clock Phase Adjustment. Larger values mean more delay. (1 LSB = T/32) Places the clamp signal an integer number of clock periods after the trailing edge of the Hsync signal. Number of clock periods that the clamp signal is actively clamping. Sets the number of pixel clocks that HSOUT will remain active. Controls the ADC input range (contrast) of each respective channel. Greater values give less contrast. Controls dc offset (brightness) of each respective channel. Greater values decrease brightness. Bit 7--Hsync Polarity Override. (Logic 0 = polarity determined by chip, Logic 1 = polarity set by Bit 6 in Register 0x0E.) Bit 6--Hsync Input Polarity. Indicates polarity of incoming Hsync signal to the PLL. (Logic 0 = active low, Logic 1 = active high.) Bit 5--Hsync Output Polarity. (Logic 0 = logic high sync, Logic 1 = logic low sync.) Bit 4--Active Hsync Override. If set to Logic 1, the user can select the Hsync to be used via Bit 3. If set to Logic 0, the active interface is selected via Bit 6 in Register 0x14. Bit 3--Active Hsync Select. Logic 0 selects Hsync as the active sync. Logic 1 selects sync-on-green as the active sync. Note that the indicated Hsync is used only if Bit 4 is set to Logic 1 or if both syncs are active. (Bits 1, 7 = Logic 1 in Register 0x14.) Bit 2--Vsync Output Invert. (Logic 1 = no invert, Logic 0 = invert.) Bit 1--Active Vsync Override. If set to Logic 1, the user can select the Vsync to be used via Bit 0. If set to Logic 0, the active interface is selected via Bit 3 in Register 0x14. Bit 0--Active Vsync Select. Logic 0 selects raw Vsync as the output Vsync. Logic 1 selects sync separated Vsync as the output Vsync. Note that the indicated Vsync is used only if Bit 1 is set to Logic 1. Bit 7--Clamp Function. Chooses between Hsync for clamp signal or another external signal to be used for clamping. (Logic 0 = Hsync, Logic 1 = Clamp.)
****0***
*****0** ******0*
*******0
0x0F
R/W
7:1
0*******
Rev. 0 | Page 17 of 32
AD9985A
Hexadecimal Address Write and Read or Read-Only Bits Default Value *1****** **0***** ***0**** ****1*** *****1** ******1* 0x10 R/W 7:3 10111*** *****0** ******0* *******0 0x11 R/W 7:0 00100000 Sync Separator Threshold Sync-on-Green Threshold Register Name Function Bit 6--Clamp Polarity. Valid only with external clamp signal. (Logic 0 = active high, Logic 1 selects active low.) Bit 5--Coast Select. Logic 0 selects the COAST input pins to be used for the PLL coast. Logic 1 selects Vsync to be used for the PLL coast. Bit 4--Coast Polarity Override. (Logic 0 = polarity determined by chip, Logic 1 = polarity set by Bit 3 in Register 0x0F.) Bit 3--Coast Polarity. Selects polarity of external Coast signal (Logic 0 = active low, Logic 1 = active high). Bit 2--Seek Mode Override (Logic 1 = allow low power mode, Logic 0 = disallow low power mode). Bit 1--PWRDN. Full Chip Power-Down, Active Low (Logic 0 = full chip power-down, Logic 1 = normal). Sync-on-Green Threshold. Sets the voltage level of the sync-ongreen slicer's comparator. Bit 2--Red Clamp Select. Logic 0 selects clamp to ground. Logic 1 selects clamp to midscale (voltage at Pin 37). Bit 1--Green Clamp Select. Logic 0 selects clamp to ground. Logic 1 selects clamp to midscale (voltage at Pin 37). Bit 0-- Blue Clamp Select. Logic 0 selects clamp to ground. Logic 1 selects clamp to midscale (voltage at Pin 37). Sync Separator Threshold. Sets the number of internal 5 MHz clock periods the sync separator counts to before toggling high or low. This should be set to some number greater than the maximum Hsync or equalization pulse width. Pre-Coast. Sets the number of Hsync periods that Coast becomes active prior to Vsync. Post-Coast. Sets the number of Hsync periods that Coast stays active following Vsync. Bit 7--Hsync detect. It is set to Logic 1 if Hsync is present on the analog interface; otherwise it is set to Logic 0. Bit 6--AHS: Active Hsync. This bit indicates which analog Hsync is being used (Logic 0 = Hsync input pin, Logic 1 = Hsync from sync-on-green). Bit 5--Input Hsync Polarity Detect (Logic 0 = active low, Logic 1 = active high). Bit 4--Vsync Detect. It is set to Logic 1 if Vsync is present on the analog interface; otherwise it is set to Logic 0. Bit 3--AVS: Active Vsync. This bit indicates which analog Vsync is being used (Logic 0 = Vsync input pin, Logic 1 = Vsync from sync separator). Bit 2--Output Vsync Polarity Detect (Logic 0 = active low, Logic 1 = active high). Bit 1--Sync-on-Green Detect. It is set to Logic 1 if sync is present on the green video input; otherwise it is set to 0. Bit 0--Input Coast Polarity Detect (Logic 0 = active low, Logic 1 = active high). Bits [7:2] Reserved for future use. Must be written to 111111 for proper operation. Bit 1--4:2:2 Output Formatting Mode (Logic 0 = 4:2:2 mode, Logic 1= 4:4:4 mode). Bit 0--Must be set to 0 for proper operation.
0x12 0x13 0x14
R/W R/W RO
7:0 7:0 7:0
00000000 00000000
Pre-Coast Post-Coast Sync Detect
0x15
R/W
7:2 1 0
111111** ******1* *******1
Reserved Output Formats Reserved
Rev. 0 | Page 18 of 32
AD9985A
Hexadecimal Address 0x16 Write and Read or Read-Only R/W Bits 7 6:5 Default Value 0******* *00***** Register Name Extra PLL Divider SOGIN Bandwidth Control Analog Input Bandwidth Control Reserved Test Register Test Register Red Target Code Green Target Code Blue Target Code Reserved Auto Offset Enable Hold Auto Offset Reserved Update Mode Test Register Function Bit 7--Extra PLL Divider. (Logic 0 = off, Logic 1 = extra divide-by-2). Bits [6:5]--SOGIN Bandwidth Control; 00 = 300 MHz; 01 or 10 = 13 MHz; 11 = 6.5 MHz. Bit 4--Sets the bandwdith of the red, green and blue analog inputs. (Logic 0 = 300 MHz, Logic 1 = 7 MHz). Reserved. Reserved. Reserved. Target Code for Auto-Offset Operation. Target Code for Auto-Offset Operation. Target Code for Auto-Offset Operation. Must be written to 0x11 for proper operation. Enables the auto-offset circuitry. Holds the offset output of the auto-offset at the current value. Must be written to 9 for proper operation. Changes the update rate of the auto-offset. Must be set to default value.
4
***0****
0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D
RO RO R/W R/W R/W R/W R/W
3:0 7:0 7:0 7:0 7:0 7:0 7:0 7 6 5:2 1:0 7:0
****0000
00000100 00000100 00000100 00010001 0******* *0****** **1001** ******10 0000****
0x1E
1
R/W
The AD9985A only updates the PLL divide ratio when the LSBs are written to (Register 0x02).
2-WIRE SERIAL CONTROL REGISTER DETAIL CHIP IDENTIFICATION
00 7-0 Chip Revision An 8-bit register that represents the silicon revision.
VESA has established some standard timing specifications that assist in determining the value for PLLDIV as a function of horizontal and vertical display resolution and frame rate (Table 8). However, many computer systems do not conform precisely to the recommendations, and these numbers should be used only as a guide. The display system manufacturer should provide automatic or manual means for optimizing PLLDIV. An incorrectly set PLLDIV usually produces one or more vertical noise bars on the display. The greater the error, the greater the number of bars produced. The power-up default value of PLLDIV is 1693 (PLLDIVM = 0x69, PLLDIVL = 0xDx). The AD9985A updates the full-divide ratio only when the LSBs are changed. Writing to the MSB by itself does not trigger an update. 02 7-4 PLL Divide Ratio LSBs The 4 least significant bits of the 12-bit PLL divide ratio PLLDIV. The operational divide ratio is PLLDIV + 1.
PLL DIVIDER CONTROL
01 7-0 PLL Divide Ratio MSBs The 8 most significant bits of the 12-bit PLL divide ratio PLLDIV. (The operational divide ratio is PLLDIV + 1.) The PLL derives a master clock from an incoming Hsync signal. The master clock frequency is then divided by an integer value, such that the output is phase-locked to Hsync. This PLLDIV value determines the number of pixel times (pixels plus horizontal blanking overhead) per line. This is typically 20% to 30% more than the number of active pixels in the display. The 12-bit value of the PLL divider supports divide ratios from 2 to 4095. The higher the value loaded in this register, the higher the resulting clock frequency with respect to a fixed Hsync frequency.
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AD9985A
The power-up default value of PLLDIV is 1693 (PLLDIVM = 0x69, PLLDIVL = 0xDx). The AD9985A updates the full divide ratio only when this register is written to.
CLAMP TIMING
05 7-0 Clamp Placement An 8-bit register that sets the position of the internally generated clamp. When clamp function (Register 0x0F, Bit 7) = 0, a clamp signal is generated internally, at a position established by the clamp placement and for a duration set by the clamp duration. Clamping is started (clamp placement) pixel periods after the trailing edge of Hsync. The clamp placement can be programmed to any value between 1 and 255. The clamp should be placed during a time that the input signal presents a stable black-level reference, usually the back porch period between Hsync and the image. When clamp function = 1, this register is ignored. 06 7-0 Clamp Duration An 8-bit register that sets the duration of the internally generated clamp. For the best results, the clamp duration should be set to include the majority of the black reference signal time that follows the Hsync signal trailing edge. Insufficient clamping time can produce brightness changes at the top of the screen, and a slow recovery from large changes in the average picture level (APL), or brightness. When clamp function = 1, this register is ignored.
CLOCK GENERATOR CONTROL
03 7-6 VCO Range Select Two bits that establish the operating range of the clock generator. VCORNGE must be set to correspond with the desired operating frequency (incoming pixel rate). The PLL gives the best jitter performance at high frequencies. For this reason, to output low pixel rates and still get good jitter performance, the PLL actually operates at a higher frequency but then divides down the clock rate afterwards. Table 11 shows the pixel rates for each VCO range setting. The PLL output divisor is automatically selected with the VCO range setting. Table 11. VCO Ranges
PV1 0 0 1 1 PV0 0 1 0 1 Pixel Clock Range (MHz) AD9985AKSTZ AD9985ABSTZ 12 to 32 12 to 30 32 to 64 (power-up 30 to 60 (power-up default) default) 64 to 110 60 to 110 110 to 140
03
5-3 Current Charge Pump Current Three bits that establish the current driving the loop filter in the clock generator. Current must be set to correspond with the desired operating frequency (incoming pixel rate). 07
HSYNC PULSE WIDTH
7-0 Hsync Output Pulse Width An 8-bit register that sets the duration of the Hsync output pulse. The leading edge of the Hsync output is triggered by the internally generated, phase-adjusted PLL feedback clock. The AD9985A then counts a number of pixel clocks equal to the value in this register. This triggers the trailing edge of the Hsync output, which is also phase adjusted.
Table 12. Charge Pump Currents
CURRENT 000 001 010 011 100 101 110 111 Current (A) 50 100 (power-up default) 150 250 350 500 750 1500
INPUT GAIN
08 7-0 Red Channel Gain Adjust (REDGAIN) An 8-bit word that sets the gain of the red channel. The AD9985A can accommodate input signals with a full-scale range of between 0.5 V and 1.0 V p-p. Setting REDGAIN to 255 corresponds to a 1.0 V input range. A REDGAIN of 0 establishes a 0.5 V input range. Increasing REDGAIN results in the picture having less contrast (the input signal uses fewer of the available converter codes). See Figure 4.
04
7-3 Clock Phase Adjust A 5-bit value that adjusts the sampling phase in 32 steps across one pixel time. Each step represents an 11.25 shift in sampling phase. The power-up default value is 16.
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AD9985A
09 7-0 Green Channel Gain Adjust (GREENGAIN) An 8-bit word that sets the gain of the green channel. See REDGAIN (08). 7-0 Blue Channel Gain Adjust (BLUEGAIN) An 8-bit word that sets the gain of the blue channel. See REDGAIN (08).
MODE CONTROL 1
0E 7 Hsync Input Polarity Override This register is used to override the internal circuitry that determines the polarity of the Hsync signal going into the PLL.
0A
Table 13. Hsync Input Polarity Override Settings
Override 0 1 Result Hsync polarity determined by chip Hsync polarity determined by user
INPUT OFFSET
0B 7-1 Red Channel Offset Adjust This offset register and those that follow have two modes of operation. One mode is when the auto offset function is turned off (manual mode) and the other is when auto offset is turned on. When in manual offset adjustment mode (auto offset turned off), this register behaves exactly like the AD9883A. It is a 7-bit offset binary word that sets the dc offset of the red channel. One LSB of offset adjustment equals approximately one LSB change in the ADC offset. Therefore, the absolute magnitude of the offset adjustment scales as the gain of the channel is changed. A nominal setting of 63 results in the channel nominally clamping the back porch (during the clamping interval) to Code 00. An offset setting of 127 results in the channel clamping to Code 64 of the ADC. An offset setting of 0 clamps to Code -63 (off the bottom of the range). Increasing the value of red offset decreases the brightness of the channel. When in auto offset mode, the value in this register is digitally added to the red channel ADC output. The purpose of doing this is to match the operation with manual offset adjustment. Adjusting these registers is an easy way to make brightness adjustments. Although some signal range is lost with this method, it has proven to be a very popular function. In order to be able to increase and decrease brightness, the values in these registers in this mode are signed twos complement (vs. manual mode, where the values in this register are binary). The digital adder is used only in auto offset mode. Although it cannot be disabled, setting this register to all 0s effectively disables it by always adding 0. 0C 7-1 Green Channel Offset Adjust This register works exactly like the Red Channel Offset Adjust Register (0x0B), except it is for the green channel. 7-1 Blue Channel Offset Adjust This register works exactly like the Red Channel Offset Adjust register (0x0B), except it is for the blue channel.
The default for Hsync polarity override is 0 (polarity determined by chip). 0E 6 HSPOL Hsync Input Polarity A bit that must be set to indicate the polarity of the Hsync signal that is applied to the PLL Hsync input.
Table 14. Hsync Input Polarity Settings
Polarity 0 1 Result Active low Active high (power-up default)
Active low means the leading edge of the Hsync pulse is negative-going. All timing is based on the leading edge of Hsync, which is the falling edge. The rising edge has no effect. Active high is inverted from the traditional Hsync, with a positive-going pulse. This means that timing is based on the leading edge of Hsync, which is now the rising edge. The device operates if this bit is set incorrectly, but the internally generated clamp position, as established by clamp placement (Register 0x05), is not placed as expected, which can generate clamping errors. 0E 5 Hsync Output Polarity This bit determines the polarity of the Hsync output and the SOG output. Table 15 shows the effect of this option. SYNC indicates the logic state of the sync pulse.
Table 15. Hsync Output Polarity Settings
Polarity 0 1 Result Logic 1 (positive polarity; power-up default) Logic 0 (negative polarity)
0E
0D
4 Active Hsync Override This bit is used to override the automatic Hsync selection. To override, set this bit to Logic 1. When overriding, the active Hsync is set via Bit 3 in this register.
Rev. 0 | Page 21 of 32
AD9985A
Table 16. Active Hsync Override Settings
Override 0 1 Result Autodetermines the active interface (power-up default) Override, Bit 3 determines the active interface
Table 21. Clamp Input Signal Source Settings
Clamp Function 0 1 Result Internally generated clamp signal (powerup default) Externally provided clamp signal
0E
3 Active Hsync Select This bit is used under two conditions. It is used to select the active Hsync when the override bit is set (Bit 4). Alternately, it is used to determine the active Hsync when not overriding, but both Hsyncs are detected.
Result Hsync input (power-up default) Sync-on-green input
A 0 enables the clamp timing circuitry controlled by clamp placement and clamp duration. The clamp position and duration is counted from the leading edge of Hsync. A 1 enables the external CLAMP input pin. The three channels are clamped when the clamp signal is active. The polarity of clamp is determined by the clamp polarity bit (Register 0x0F, Bit 6). 0F 6 Clamp Input Signal Polarity This bit determines the polarity of the externally provided clamp signal.
Result Active low (power-up default) Active high
Table 17. Active Hsync Select Settings
Select 0 1
0E
2 Vsync Output Invert This bit inverts the polarity of the Vsync output Table 18 shows the effect of this option.
Vsync Output Invert (power-up default) No invert
Table 22. Clamp Input Signal Polarity Settings
Clamp Function 1 0
Table 18. Vsync Output Invert Settings
Invert 0 1
0E
1 Active Vsync Override This bit is used to override the automatic Vsync selection. To override, set this bit to Logic 1. When overriding, the active interface is set via Bit 0 in this register.
Result Autodetermines the active Vsync (power-up default) Override, Bit 0 determines the active Vsync
Logic 1 means that the circuit clamps when CLAMP is low, and it passes the signal to the ADC when CLAMP is high. Logic 0 means that the circuit clamps when CLAMP is high, and it passes the signal to the ADC when CLAMP is low. 0F 5 Coast Select This bit is used to select the active Coast source. The choices are the COAST input pin or Vsync. If Vsync is selected, the additional decision to use the Vsync input pin or the output from the sync separator needs to be made (Register 0x0E, Bits 1, 0).
Result COAST input pin Vsync (See the Coast Select section)
Table 19. Active Vsync Override Settings
Override 0 1
0E
0 Active Vsync Select This bit is used to select the active Vsync when the override bit is set (Bit 1).
Result Vsync input (power-up default) Sync separator output
Table 23. Power-Down Settings
Power-Down 0 1
Table 20. Active Vsync Select Settings
Select 0 1
0F
0F
7 Clamp Input Signal Source This bit determines the source of clamp timing.
4 Coast Input Polarity Override This register is used to override the internal circuitry that determines the polarity of the Coast signal going into the PLL.
Rev. 0 | Page 22 of 32
AD9985A
Table 24. Coast Input Polarity Override Settings
Override 0 1 Result Determined by chip (power-up default) Determined by user
10
0F
3 Coast Input Polarity This bit indicates the polarity of the Coast signal that is applied to the PLL COAST input.
Result Active low Active high (power-up default) Clamp 0 1
2 Red Clamp Select This bit determines whether the red channel is clamped to ground or to midscale. For RGB video, all three channels are referenced to ground. For YCbCr (or YUV), the Y channel is referenced to ground, but the CbCr channels are referenced to midscale. Clamping to midscale actually clamps to Pin 37.
Table 25. Coast Input Polarity Settings
Coast Polarity 0 1
Table 28. Red Clamp Select Settings
Result Clamp to ground (power-up default) Clamp to midscale (Pin 37)
Active low means that the clock generator ignores Hsync inputs when Coast is low, and continues operating at the same nominal frequency until Coast goes high. Active High means that the clock generator ignores Hsync inputs when Coast is high, and continues operating at the same nominal frequency until Coast goes low. This function needs to be used along with the Coast polarity override bit (Bit 4). 0F 2 Seek Mode Override This bit is used to either allow or disallow the low power mode. The low power mode (seek mode) occurs when there are no signals on any of the Sync inputs.
Result Allow seek mode (power-up default) Disallow seek mode
10
1 Green Clamp Select This bit determines whether the green channel is clamped to ground or to midscale.
Result Clamp to ground (power-up default) Clamp to midscale (Pin 37)
Table 29. Green Clamp Select Settings
Clamp 0 1
10
0 Blue Clamp Select This bit determines whether the blue channel is clamped to ground or to midscale.
Result Clamp to ground (power-up default) Clamp to midscale (Pin 37)
Table 30. Blue Clamp Select Settings
Clamp 0 1
11
Table 26. Seek Mode Override Settings
Override 1 0
0F
1 PWRDN This bit is used to put the chip in full power-down. See the Power Management section for details on which blocks are powered down.
Result Power-down Normal operation
7-0 Sync Separator Threshold This register is used to set the responsiveness of the sync separator. It sets the number of internal 5 MHz clock periods the sync separator must count to before toggling high or low. It works like a low-pass filter to ignore Hsync pulses in order to extract the Vsync signal. This register should be set to some number greater than the maximum Hsync pulse width. The sync separator threshold uses an internal dedicated clock with a frequency of approximately 5 MHz. The default for this register is 32. 7-0 Pre-Coast This register allows the Coast signal to be applied prior to the Vsync signal. This is necessary in cases where pre-equalization pulses are present. The step size for this control is one Hsync period. The default is 0.
Table 27. Power-Down Settings
Power-Down 0 1
12
10
7-3 Sync-on-Green Slicer Threshold This register allows the comparator threshold of the sync-on-green slicer to be adjusted. This register adjusts it in steps of 10 mV, with the minimum setting equaling 10 mV (11111) and the maximum setting equaling 330 mV (00000). The default setting is 23, which corresponds to a threshold value of 100 mV; for a threshold of 150 mV, the setting should be 18.
13
7-0 Post-Coast This register allows the Coast signal to be applied following the Vsync signal. This is necessary when post-equalization pulses are present. The step size for this control is one Hsync period. The default is 0.
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AD9985A
14 7 Hsync Detect This bit is used to indicate when activity is detected on the Hsync input pin (Pin 30). If Hsync is held high or low, activity will not be detected.
Function No activity detected Activity detected
Table 34. Vsync Detection Results
Detect 0 1 Result No activity detected Activity detected
Table 31. Hsync Detection Results
Detect 0 1
The sync processing block diagram (Figure 14) shows where this function is implemented. 14 3 Active Vsync (AVS) This bit indicates which Vsync source is being used, the Vsync input or output from the sync separator. Bit 4 in this register determines which is active. If both Vsync and SOG are detected, the user can determine which has priority via Bit 0 in Register 0x0E. The user can override this function via Bit 1 in Register 0x0E. If the override bit is set to Logic 1, this bit is set to the state of Bit 0 in Register 0x0E.
Bit 1, Reg. 0x 0E (Override) 0 0 1 AVS 0 1 Bit 0 in 0x0E
The sync processing block diagram (Figure 14) shows where this function is implemented. 14 6 Active Hsync (AHS) This bit indicates which Hsync input source is being used by the PLL (Hsync input or sync-on-green). Bit 7 and Bit 1 in this register determine which source is used. If both Hsync and SOG are detected, the user can determine which has priority via Bit 3 in Register 0x0E. The user can override this function via Bit 4 in Register 0x0E. If the override bit is set to Logic 1, then this bit is set to the state of Bit 3 in Register 0x0E.
Bit 1 (SOG Detect) 0 1 0 1 X Bit 4 Reg. 0x0E (Override) 0 0 0 0 1
Table 35. Active Vsync Results
Bit 4, Reg 14H (Vsync Detect) 1 0 X
Table 32. Active Hsync Results
Bit 7 (Hsync Detect) 0 0 1 1 X
AVS = 0 means Vsync input. AVS = 1 means Sync separator.
AHS Bit 3 in 0x0E 1 0 Bit 3 in 0x0E Bit 3 in 0x0E
The override bit is in Register 0x0E, Bit 1. 14 2 Detected Vsync Output Polarity Status This bit reports the status of the Vsync output polarity detection circuit. It can be used to determine the polarity of the Vsync output. The detection circuit's location is shown in the sync processing block diagram (Figure 14).
Result Active low Active high
AHS = 0 means use the Hsync pin input for Hsync. AHS = 1 means use the SOG pin input for Hsync. The override bit is in Register 0x0E, Bit 4. 14 5 Detected Hsync Input Polarity Status This bit reports the status of the Hsync input polarity detection circuit. It can be used to determine the polarity of the Hsync input. The detection circuit's location is shown in the sync processing block diagram (Figure 14).
Result Negative Positive
Table 36. Detected Vsync Output Polarity Status
Vsync Polarity Status 0 1
14
1 Sync-on-Green Detect This bit is used to indicate when sync activity is detected on the sync-on-green input pin (Pin 49). Table 37. Sync-on-Green Detection Results
Detect 0 1 Result No activity detected Activity detected
Table 33. Detected Hsync Input Polarity Status
Hsync Polarity Status 0 1
14
4
Vsync Detect 14
The sync processing block diagram (Figure 14) shows where this function is implemented. 0 Detected Coast Polarity Status This bit reports the status of the Coast input polarity detection circuit. It can be used to determine the polarity of the Coast input. The detection circuit's location is shown in the sync processing block diagram (Figure 14).
This bit is used to indicate when activity is detected on the Vsync input pin (Pin 31). If Vsync is held steady high or low, activity is not detected.
Rev. 0 | Page 24 of 32
AD9985A
Table 38. Detected Coast Input Polarity Status
Polarity Status 0 1 Result Coast polarity negative Coast polarity positive
16
4
Analog Input Bandwidth
This indicates that Bit 1 of Register 5 is the 4:2:2 output mode select bit. 15 1 4:2:2 Output Mode Select
Select 0 1
This bit controls the bandwidth of the red, green, and blue analog inputs. In most applications, the analog input bandwidth should be set to its maximum (300 MHz). When there is excessive noise on the analog inputs, reducing the bandwidth can help suppress the noise. Table 43. Anti-Aliasing Filter
Input Bandwidth 300 MHz 7 MHz
A bit that configures the output data in 4:2:2 mode. This mode can be used to reduce the number of data lines used from 24 down to 16 for applications using YUV, YCbCr, or YPbPr graphics signals. A timing diagram for this mode is shown in Figure 11. Recommended input and output configurations are shown in Table 39 and Table 40. Table 39. 4:2:2 Output Mode Select
Select 0 1 Output Mode 4:2:2 4:4:4
19
7:0
Red Target Code
This specifies the targeted value of the final offset for the red channel when auto-offset is used (Register 0x1D, Bit 7 = 1). Default is 4. 1A 7:0 Green Target Code
Table 40. 4:2:2 Input/Output Configuration
Channel Red Green Blue Input Connection V Y U Output Format U/V Y High impedance
This specifies the targeted value of the final offset for the green channel when auto-offset is used (Register 0x1D Bit 7 = 1). Default is 4. 1B 7:0 Blue Target Code
16
7
Extra PLL Divider 1D
This specifies the targeted value of the final offset for the blue channel when auto-offset is used (Register 0x1D, Bit 7 = 1). Default is 4. 7 Auto-Offset Enable
A bit that can add an additional divide-by-2 into the PLL divide ratio. Enabling this function at pixel frequencies below 20 MHz can result in improved PLL jitter performance, as it allows the VCO to run at a higher frequency, resulting in lower jitter. Table 41. PLL VCO Divide
Select 0 1 PLL Divider Off Extra divide-by-2
Enables the auto-offset circuitry. Default is 0. 1D 6 Hold Auto-Offset
Holds the offset output of the auto-offset at the current value. Default is 0. 1D 1:0 Update Mode
16
6-5
SOGIN Bandwidth
Changes the update rate of the auto-offset. Default is 10. Table 44. Auto-Offset Update Rate
Update Mode 00 01 10 Auto-Offset Update Timing Every clamp cycle Every 16 clamp cycles Every 64 camp cycles
Two bits that can control the bandwidth of the syncon-green input (SOGIN). In most applications, the SOGIN bandwidth should be set to its maximum (300 MHz). When there is excessive noise on SOGIN, reducing the bandwidth can help suppress the noise. Table 42. SOGIN Bandwidth
Select 00 01 or 10 11 Pulses Filtered 300 MHz 13 MHz 6.5 MHz
Rev. 0 | Page 25 of 32
AD9985A 2-WIRE SERIAL CONTROL PORT
A 2-wire serial interface control interface is provided. Two AD9985A devices can be connected to the 2-wire serial interface; each device has a unique address. The 2-wire serial interface comprises a clock (SCL) and a bidirectional data (SDA) pin. The analog flat panel interface acts as a slave for receiving and transmitting data over the serial interface. When the serial interface is not active, the logic levels on SCL and SDA are pulled high by external pull-up resistors. Data received or transmitted on the SDA line must be stable for the duration of the positive-going SCL pulse. Data on SDA must change only when SCL is low. If SDA changes state while SCL is high, the serial interface interprets that action as a start or stop sequence. The components to serial bus operation are * * * * * Start signal Slave address byte Base register address byte Data byte to read or write Stop signal
DATA TRANSFER VIA SERIAL INTERFACE
For each byte of data read or written, the MSB is the first bit of the sequence. If the AD9985A does not acknowledge the master device during a write sequence, the SDA remains high so the master can generate a stop signal. If the master device does not acknowledge the AD9985A during a read sequence, the AD9985A interprets this as end-of-data. The SDA remains high so the master can generate a stop signal. Writing data to specific control registers of the AD9985A requires that the 8-bit address of the control register of interest be written after the slave address has been established. This control register address is the base address for subsequent write operations. The base address auto-increments by one for each byte of data written after the data byte intended for the base address. Data is read from the control registers of the AD9985A in a similar manner. Reading requires two data transfer operations: The base address must be written with the R/W bit of the slave address byte low to set up a sequential read operation. Reading (the R/W bit of the slave address byte high) begins at the previously established base address. The address of the read register auto-increments after each byte is transferred. To terminate a read/write sequence to the AD9985A, a stop signal must be sent. A stop signal comprises a low-to-high transition of SDA while SCL is high. A repeated start signal occurs when the master device driving the serial interface generates a start signal without first generating a stop signal to terminate the current communication. This is used to change the mode of communication (read, write) between the slave and master without releasing the serial interface lines.
When the serial interface is inactive (SCL and SDA are high), communications are initiated by sending a start signal. The start signal is a high-to-low transition on SDA while SCL is high. This signal alerts all slave devices that a data transfer sequence is coming. The first eight bits of data transferred after a start signal comprise a 7-bit slave address (the first seven bits) and a single R/W bit (the eighth bit). The R/W bit indicates the direction of data transfer, read from (1) or write to (0) the slave device. If the transmitted slave address matches the address of the device (set by the state of the SA1-0 input pins in Table 45), the AD9985A acknowledges by bringing SDA low on the ninth SCL pulse. If the addresses do not match, the AD9985A does not acknowledge. Table 45. Serial Port Addresses
Bit 7 A6 (MSB) 1 1 Bit 6 A5 0 0 Bit 5 A4 0 0 Bit 4 A3 1 1 Bit 3 A2 1 1 Bit 2 A1 0 0 Bit 1 A0 0 1
SDA
tBUFF tSTAH
SCL
tDHO tDAL
tDSU
tSTASU
tSTOSU
tDAH
Figure 12. Serial Port Read/Write Timing
Rev. 0 | Page 26 of 32
05484-012
AD9985A
Serial Interface Read/Write Examples Write to one control register: 1. 2. 3. 4. 5. Start signal Slave address byte (R/W Bit = low) Base address byte Data byte to base address Stop signal Read from one control register: 1. 2. 3. 4. 5. 6. 7. Start signal Slave address byte (R/W bit = low) Base address byte Start signal Slave address byte (R/W bit = high) Data byte from base address Stop signal
Write to four consecutive control registers: 1. 2. 3. 4. 5. 6. 7. 8. Start signal Slave address byte (R/W bit = low) Base address byte Data byte to base address Data byte to (base address + 1) Data byte to (base address + 2) Data byte to (base address + 3) Stop signal Read from four consecutive control registers: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
Start signal Slave address byte (R/W bit = low) Base address byte Start signal Slave address byte (R/W Bit = high) Data byte from base address Data byte from (base address + 1) Data byte from (base Address + 2) Data byte from (base Address + 3) Stop signal
BIT 1 BIT 0 ACK
05484-014
SDA
SCL
Figure 13. Serial Interface--Typical Byte Transfer
SYNC STRIPPER NEGATIVE PEAK CLAMP SOG COMP SYNC
ACTIVITY DETECT
SYNC SEPARATOR INTEGRATOR 1/S MUX 1 VSYNC
HSYNC IN
SOG OUT PLL ACTIVITY DETECT POLARITY DETECT
HSYNC MUX 2 COAST COAST MUX 3 POLARITY DETECT CLOCK GENERATOR
HSYNC OUT PIXEL CLOCK
HSYNC OUT
AD9985A
VSYNC IN
VSYNC OUT
05484-015
ACTIVITY DETECT
POLARITY DETECT
MUX 4
Figure 14. Sync Processing Block Diagram
Rev. 0 | Page 27 of 32
AD9985A
Table 46. Control of the Sync Block Muxes via the Serial Register
Mux No. 1 and 2 3 4 Serial Bus Control Bit 0x0E: Bit 3 0x0F: Bit 5 0x0E: Bit 0 Control Bit State 0 1 0 1 0 1 Result Pass Hsync Pass sync-on-green Pass Coast Pass Vsync Pass Vsync Pass sync separator signal
SYNC SLICER
The purpose of the sync slicer is to extract the sync signal from the green graphics channel. A sync signal is not present on all graphics systems, only those with sync-on-green. The sync signal is extracted from the green channel in a two-step process. First, the SOG input is clamped to its negative peak (typically, 0.3 V below the black level). Next, the signal goes to a comparator with a variable trigger level, nominally 0.15 V above the clamped level. The sliced sync is typically a composite sync signal containing both Hsync and Vsync. The specific value of N varies for different video modes, but is always less than 255. For example, with a 1 s width Hsync, the counter only reaches 5 (1 s/200 ns = 5). Now, when Vsync is present on the composite sync, the counter also counts up. However, since the Vsync signal is much longer, it counts to a higher number M. For most video modes, M is at least 255. So, Vsync can be detected on the composite sync signal by detecting when the counter counts to a value higher than N. The specific count that triggers detection (T) can be programmed through the serial register (0x11). Once Vsync has been detected, there is a similar process to detect when it goes inactive. At detection, the counter first resets to 0, then starts counting up when Vsync goes away. Similar to the previous case, it detects the absence of Vsync when the counter reaches the threshold count (T). In this way, it rejects noise and/or serration pulses. Once Vsync is detected to be absent, the counter resets to 0 and begins the cycle again.
SYNC SEPARATOR
A sync separator extracts the Vsync signal from a composite sync signal. It does this through a low-pass filter-like or integrator-like operation. It works on the idea that the Vsync signal stays active for a much longer time than the Hsync signal, so it rejects any signal shorter than a threshold value, which is somewhere between an Hsync pulse width and a Vsync pulse width. The sync separator on the AD9985A is simply an 8-bit digital counter with a 5 MHz clock. It works independently of the polarity of the composite sync signal. (Polarities are determined elsewhere on the chip.) The basic idea is that the counter counts up when Hsync pulses are present. But since Hsync pulses are relatively short in width, the counter only reaches a value of N before the pulse ends. It then starts counting down, eventually reaching 0 before the next Hsync pulse arrives.
Rev. 0 | Page 28 of 32
AD9985A PCB LAYOUT RECOMMENDATIONS
The AD9985A is a high precision, high speed analog device. Consequently, to get the maximum performance out of the part, it is important to have a board with a good layout. This section provides guidelines for designing a board using the AD9985A. The bypass capacitors should be physically located between the power plane and the power pin. Current should flow from the power plane to the capacitor to the power pin. Do not make the power connection between the capacitor and the power pin. Placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. It is particularly important to maintain low noise and good stability of PVD (the clock generator supply). Abrupt changes in PVD can result in similarly abrupt changes in sampling clock phase and frequency. This can be avoided by careful attention to regulation, filtering, and bypassing. It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (VD and PVD). Some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). This can result in a measurable change in the voltage supplied to the analog supply regulator, which can, in turn, produce changes in the regulated analog supply voltage. This can be mitigated by regulating the analog supply, or at least PVD, from a different, cleaner power source (for example, from a 12 V supply). It is recommended to use a single ground plane for the entire board. Experience has repeatedly shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. When using separate ground planes is unavoidable, it is recommended to minimally place a single ground plane under the AD9985A. The location of the split should be at the receiver of the digital outputs. For this case, it is even more important to place components wisely because the current loops are much longer (current takes the path of least resistance). Figure 15 shows an example of a current loop.
DP UN RO G
E LAN
POWER PLANE
ANALOG INTERFACE INPUTS
Using the following layout techniques on the graphics inputs is extremely important. Minimize the trace length running into the graphics inputs. This is accomplished by placing the AD9985A as close as possible to the graphics VGA connector. Long input trace lengths are undesirable because they pick up more noise from the board and other external sources. Place the 75 termination resistors (see Figure 1) as close as possible to the AD9985A chip. Any additional trace length between the termination resistors and the input of the AD9985A increases the magnitude of reflections, which corrupts the graphics signal. Use 75 matched impedance traces. Trace impedances other than 75 also increase the chance of reflections. The AD9985A has very high input bandwidth (500 MHz). While this is desirable for acquiring a high resolution PC graphics signal with fast edges, it means that it also captures any high frequency noise present. Therefore, it is important to reduce the amount of noise that is coupled to the inputs. Avoid running any digital traces near the analog inputs. Due to the high bandwidth of the AD9985A, low-pass filtering the analog inputs can sometimes help to reduce noise. (For many applications, filtering is unnecessary.) Experiments have shown that placing a series ferrite bead prior to the 75 termination resistor is helpful in filtering out excess noise. Specifically, the part used was the #2508051217Z0 from FairRite, but each application can work best with a different bead value. Alternately, placing a 100 to 120 resistor between the 75 termination resistor and the input coupling capacitor can also be beneficial.
AD998 5A
DI GI T
TPUT T OU RA AL
DI
It is recommended to bypass each power supply pin with a 0.1 F capacitor. The exception is when two or more supply pins are adjacent to each other. For these groupings of powers/ grounds, it is necessary to have only one bypass capacitor. The fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the AD9985A, as that interposes resistive vias in the path.
GR
OUN
D PL A
NE
DIGITAL DATA R
ECEIV
ER
Figure 15. Current Loop
PLL
Place the PLL loop filter components as close to the FILT pin as possible. Do not place any digital or other high frequency traces near these components. Use the values suggested in the data sheet with 10% tolerances or less.
Rev. 0 | Page 29 of 32
05484-016
GI
TA L
CE
POWER SUPPLY BYPASSING
ANALO G
AD9985A
OUTPUTS (BOTH DATA AND CLOCKS)
Try to minimize the trace length that the digital outputs have to drive. Longer traces have higher capacitance, which requires more current, which causes more internal digital noise. Shorter traces reduce the possibility of reflections. Adding a series resistor of value 22 to 100 can suppress reflections, reduce EMI, and reduce the current spikes inside of the AD9985A. However, if 50 traces are used on the PCB, the data outputs should not need resistors. A 22 resistor on the DATACK output should provide good impedance matching that reduces reflections. If series resistors are used, place them as close as possible to the AD9985A pins (but try not to add vias or extra length to the output trace in order to get the resistors closer). If possible, limit the capacitance that each of the digital outputs drives to less than 10 pF. This can easily be accomplished by keeping traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current transients inside of the AD9985A, creating more digital noise on its power supplies.
DIGITAL INPUTS
The digital inputs on the AD9985A were designed to work with 3.3 V signals, but are tolerant of 5.0 V signals. Therefore, no extra components need to be added if using 5.0 V logic. Any noise that gets onto the Hsync input trace adds jitter to the system. Therefore, minimize the trace length and do not run any digital or other high frequency traces near it.
VOLTAGE REFERENCE
Bypass the voltage reference with a 0.1 F capacitor. Place it as close as possible to the AD9985A pin. Make the ground connection as short as possible.
Rev. 0 | Page 30 of 32
AD9985A OUTLINE DIMENSIONS
0.75 0.60 0.45 1.60 MAX
80 1 PIN 1
16.20 16.00 SQ 15.80
61 60
TOP VIEW (PINS DOWN)
14.20 14.00 SQ 13.80
1.45 1.40 1.35
0.15 0.05
SEATING PLANE
0.20 0.09 7 3.5 0 0.10 MAX COPLANARITY
20 21 40
41
VIEW A
VIEW A
ROTATED 90 CCW
0.65 BSC LEAD PITCH
0.38 0.32 0.22
COMPLIANT TO JEDEC STANDARDS MS-026-BEC
Figure 16. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9985ABSTZ-110 1 AD9985AKSTZ-1101 AD9985AKSTZ-1401 AD9985A/PCB
1
Temperature Range -40C to +85C 0C to 70C 0C to 70C
Package Description 80-lead LQFP 80-lead LQFP 80-lead LQFP Evaluation Board
Package Option ST-80-2 ST-80-2 ST-80-2
Z = Pb-free part.
Rev. 0 | Page 31 of 32
AD9985A NOTES
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05484-0-7/05(0)
Rev. 0 | Page 32 of 32

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